2 posts tagged with "trace-processor"

This week, the Leios team focused on improving simulation analysis, conducting validation time studies, and working on comprehensive protocol variant experiments. The team developed new analysis tools, conducted fundamental performance studies of Cardano validation times, and completed extensive mapping of Linear Leios protocol performance under various conditions.

Analysis tools and infrastructure​

Generic trace analysis framework​

• Developed a generic analysis script for processing Leios simulator output
• Created a comprehensive R-based analysis pipeline generating diagnostic plots from leios-simulation-trace-processor output
• Enhanced analysis capabilities for systematic evaluation of simulation results
• Documentation and usage instructions are available in the trace processor README.

Validation performance analysis​

Cardano mainnet validation timing study​

• Completed a preliminary analysis of block and transaction validation times for Cardano mainnet since epoch 350
• Key findings using the db-analyser tool include:
  • Median transaction signature verification: 0.53 ms/tx
  • Median validation time per kilobyte: 0.29 ms/kB
  • Joint linear model estimate: 0.066 ms/tx plus 0.221 ms/kB
  • Data suitable for bulk estimates but too noisy for individual transaction predictions
• Identified missing explanatory variables (UTXO set size, input/output counts) extractable from the ledger or cardano-db-sync
• Results provide a foundation for more accurate simulator validation time modeling
• Detailed analysis is available in the validation timing notebook.

Simulation optimization studies​

Timestep resolution analysis​

• Conducted a comparative study of simulation timestep effects at 1,000 TPS Full Leios scenarios
• Compared 0.100 ms and 0.025 ms time resolutions with no significant differences in results
• Validated the use of coarser timesteps for improved parallelism and reduced simulation runtime
• Supporting analysis and evidence are available in the timestep study notebook.

Protocol variant experiments​

Mid-throughput protocol validation​

• Completed 100 TPS experiments for Stracciatella and Linear Leios variants using 1,400 B/tx over 900 seconds
• Key findings include:
  • 5 slots/stages are insufficient for Linear Leios at 100 tx/s
  • Including transactions in EBs causes congestion compared to transaction references
  • 10 MB/EB is required for 100 tx/s performance (5 MB/EB is insufficient)
  • EB-sortition unluckiness in Stracciatella extends the transaction lifecycle but can be mitigated
  • CPU and network peaks occur when transactions are embedded in EBs
• Analysis artifacts are available in 100 TPS experiment documentation and the analysis notebook.

Comprehensive Linear Leios performance mapping​

• Completed an extensive simulation study mapping Linear Leios performance under various loads and configurations
• Compared multiple Linear Leios variants against the Stracciatella baseline
• Generated comprehensive performance characterizations across different throughput scenarios
• Results are documented in the Linear Leios summary with variant-specific analysis:
  • Linear Leios with embedded transactions
  • Linear Leios with transaction references
  • Linear Leios without transactions
  • Stracciatella baseline comparison.

Simulation model refinements​

• Revised the Linear Leios model based on analysis findings, particularly regarding partial EB validation before peer propagation
• Reimplemented Stracciatella as a separate simulation to identify specification deviations
• Identified and resolved multiple implementation inconsistencies during the specification verification process.

Next steps​

• Continue developing analysis infrastructure for systematic protocol evaluation
• Integrate improved validation timing models into simulation configurations
• Expand protocol variant testing based on performance mapping results
• Refine simulation models for enhanced accuracy and specification compliance.

This week, the Leios team focused on improving simulation analysis tools and creating more practical network topologies. Key achievements include enhancing the trace processor with additional data extraction capabilities and developing a smaller, more efficient 'miniature mainnet' topology for repeated experimentation.

Trace processor enhancements​

• Enhanced the leios-trace-processor to extract CPU, resource, and message-receipt data from simulation trace files
• Eliminated the need for using older, lower-performance scripts for analyzing simulation results
• Added comprehensive data output options:
  • Transaction lifecycle data
  • CPU utilization metrics
  • Resource consumption data
  • Message receipt tracking
• Improved analysis efficiency for large simulation datasets.

Miniature mainnet topology​

• Created a more practical 750-node topology that faithfully mimics mainnet characteristics while addressing performance limitations of the 10,000-node pseudo-mainnet
• Achieved a network diameter, stake distribution, and edge degree closely matching those of the mainnet
• Key network metrics:
  • 216 block producers and 534 relay nodes
  • 19,314 total connections with 5-hop network diameter
  • Average of 25.75 connections per node
  • Clustering coefficient of 0.332
  • Average latency of 64.8ms with maximum of 578.3ms
  • 84.85% asymmetry ratio
• Documented the methodology and results in topology-v2.ipynb
• Deployed the network configuration in topology-v2.yaml
• Enabled more practical, repeatable experimentation with realistic network characteristics.